1. Field of the Invention
The present invention relates to a semiconductor device and its manufacturing method. In particular, the invention relates to a semiconductor device in which trench lateral power MOSFETs and planar devices such as planar MOSFETs are integrated on the same semiconductor substrate as well as its manufacturing method.
2. Description of the Related Art
In power MOSFETs, in general, an extended drain region is formed to increase the breakdown voltage. FIG. 265 is a vertical sectional view showing the configuration of a conventional n-channel planar power MOSFET. As shown in FIG. 265, an n-type extended drain region 12 is provided between gate electrodes 16 of adjoining devices that share an n-type drain region 13 and a drain electrode 17, to extend parallel with the surface of a p-type semiconductor substrate 11 and surround the drain region 13. P-type base regions 14, n-type source regions 15, and source electrodes 18 are separated by placement on both sides of the extended drain region 12.
The gate electrodes 16 extend to cover a thick field oxide film 10 that is continuous with a gate oxide film 19 and serve as field plates. It is noted that in this specification the term “planar device” does not include power devices such as the planar power MOSFET.
The planar power MOSFET is manufactured by approximately the same process as planar devices such as BiCMOS. Therefore, a one-chip power IC is readily obtained by forming planar power MOSFETs and planar devices on the same semiconductor substrate. However, such a one-chip power IC including planar power MOSFETs and planar devices has a disadvantage of a low integration density because, as described above, the extended drain region 12 extends parallel with the substrate surface in the planar power MOSFET
In view of the above, a trench lateral power MOSFET (hereinafter abbreviated as “TLPM”) has been proposed which is advantageous since the on-resistance per unit area is lower than the planar power MOSFET. FIG. 266 is a vertical sectional view showing the configuration of a conventional n-channel TLPM. A trench 30 is formed in a p-type semiconductor substrate 21. An n-type extended drain region 22 is provided adjacent to the bottom surface and a bottom portion of the side surface of the trench 30.
A p-type body region 24 is provided outside the extended drain region 22, and an n-type drain region 23 is provided inside the extended drain region 22. Sequentially, a gate oxide film 29, gate electrodes 26, an interlayer insulating film 31, and a drain polysilicon layer 32 are provided inside the trench 30 from the outside. P-type channel regions 33 are provided on both sides of the trench 30, and n-type source regions 25 are provided on the respective p-type channel regions 33. P-type plug regions 34 are provided outside the respective source regions 25. Each source electrode 28 is in contact with both of the associated source region 25 and plug region 34. A drain electrode 27 is electrically connected to the drain region 23 via the drain polysilicon layer 32.
A description of a manufacturing process of the TLPM shown in FIG. 266 follows. FIGS. 267-274 are vertical sectional views showing intermediate states of manufacture of the TLPM of FIG. 266. First, a mask oxide film 41 is formed on the surface of a semiconductor substrate 21, and a trench 30 is formed through an opening of the mask oxide film 41 by RIE (reactive ion etching) (see FIG. 267). After a buffer oxide film 42 is formed on the surface of the trench 30, the semiconductor substrate 21 is doped with B11 (see FIG. 268), whereby a body region 24 is formed. The semiconductor substrate 21 is then doped with P31 (see FIG. 269) to form an extended drain region 22. After removing the buffer oxide film 42, a gate oxide film 29 is formed inside the trench 30 (see FIG. 270).
Subsequently, a polysilicon layer 43 is deposited inside the trench 30 and on the substrate surface (see FIG. 271) and then is etched back to leave only portions (as gate electrodes 26) on both side surfaces of the trench 30 (see FIG. 272). Then, an interlayer insulating film 31 is laid using a film forming method, for example, LPCVD or P-TEOS CVD. The interlayer insulating film 31 is thinner at the bottom of the trench 30 than on the substrate surface (see FIG. 273). The interlayer insulating film 31 is etched back to form a contact hole that penetrates through the interlayer insulating film 31 and the gate oxide film 29 at the bottom of the trench 30.
A drain region 23 is formed under the trench 30 through the contact hole that has been formed at the bottom of the trench 30. Then, the central portion of the trench 30 is filled with a drain polysilicon layer 32 (see FIG. 274). Then, contact holes are formed through portions of the interlayer insulating film 31 which cover the substrate surface, and channel regions 33, source regions 25, and plug regions 34 are formed. Finally, source electrodes 28 and a drain electrode 27 are formed by patterning a metal film. A TLPM having the configuration of FIG. 266 is thus completed.
In the above-type (called a “first type”) of TLPM, the drain region 23 is provided under the trench 30. Another type (called a “second type”) of TLPM is known in which a source region is provided under a trench 30. As shown in FIG. 275, in the second type of TLPM, an n-type source region 25 is provided under a trench 30 that is formed in a p-type semiconductor substrate 21. A p-type base region 45 is provided adjacent to the bottom surface and a bottom portion of the side surface of the trench 30 to surround the source region 25.
N-type extended drain regions 22 are provided on both sides of the trench 30. N-type drain regions 23 are positioned in surface layers of the extended drain regions 22, respectively. A gate oxide film 29, gate electrodes 26, an interlayer insulating film 31, and a source polysilicon layer 46 are positioned sequentially inside the trench 30 from the outside. The source electrode 28 is electrically connected with the source region 25 via the source polysilicon layer 46. Drain electrodes 27 are in contact with the respective drain regions 23.
As described above, in the first type of TLPM, the gate electrodes 26 are provided outside the drain polysilicon layer 32 with the interlayer insulating film 31 interposed between, and the extended drain region 22 is provided outside the gate electrodes 26 with the gate oxide film 29 interposed between. Therefore, in the first type of TLPM, gate-drain feedback capacitance, which is a factor of impairing the switching characteristic, exists not only between the extended drain region 22 and the gate electrodes 26, but also between the drain polysilicon layer 32 and the gate electrodes 26. On the other hand, in the second type of TLPM, gate-drain feedback capacitance exists only between the extended drain regions 22 and the gate electrodes 26. Therefore, the second type of TLPM is advantageous over the first type of TLPM since the switching characteristic is improved greatly.
However, the process that was described above for the first type of TLPM is a process for manufacturing a TLPM itself and is not compatible with manufacturing processes of planar devices such as the general CMOS and the BiCMOS. A manufacturing method of the second type TLPM, which was not described above, is approximately the same as the manufacturing method of the first type TLPM and is not compatible with manufacturing processes of planar devices, for example, the general CMOS and the BiCMOS. Therefore, conventionally, to construct a one-chip power IC using TLPMs and planar devices, TLPMs and planar devices are manufactured by separate processes and are connected to a common printed circuit board by wire bonding to attain electrical connections between the TLPMs and the planar devices.
This causes not only a cost increase, but also disadvantages such as reduction in integration density and an increase in on-resistance by the bonding wire, offsetting the advantages of the TLPM that enable a high integration density and a low on-resistance per unit area.